{"created":"2023-05-15T12:21:02.102747+00:00","id":11804,"links":{},"metadata":{"_buckets":{"deposit":"bc84d946-6fa6-48cc-bd79-72850cd451d2"},"_deposit":{"created_by":1,"id":"11804","owners":[1],"pid":{"revision_id":0,"type":"depid","value":"11804"},"status":"published"},"_oai":{"id":"oai:kansai-u.repo.nii.ac.jp:00011804","sets":["528:1588:1628:1629"]},"author_link":["28289","28287","28290","28288"],"item_10_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2008-03-20","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"44","bibliographicPageStart":"29","bibliographicVolumeNumber":"50","bibliographic_titles":[{"bibliographic_title":"Science and technology reports of Kansai University = 関西大学理工学研究報告"}]}]},"item_10_description_4":{"attribute_name":"概要","attribute_value_mlt":[{"subitem_description":"This paper describes advanced results of our evaluation of the minimum channel length　(Lmin). For the first time, we have added the constraint of subthreshold swing to that of threshold voltage, which has already been proposed. The Lmin definition that includes the subthreshold swing constraint successfully yields a design guideline for low standby power applications, while the Lmin definition based on the threshold voltage constraint does the same for high-speed applications. In contrast to previous predictions, simulation results indicate that the planar single-gate SOI MOSFET promises better performance, clearing the ITRS roadmap until at least 2007 for low standby power applications.","subitem_description_type":"Other"}]},"item_10_description_5":{"attribute_name":"内容記述","attribute_value_mlt":[{"subitem_description":"ELECTRICAL AND ELECTRONIC ENGINEERING, 50th anniversary edition","subitem_description_type":"Other"}]},"item_10_full_name_3":{"attribute_name":"著者別名","attribute_value_mlt":[{"nameIdentifiers":[{"nameIdentifier":"28289","nameIdentifierScheme":"WEKO"}],"names":[{"name":"大村, 泰久"}]},{"nameIdentifiers":[{"nameIdentifier":"28290","nameIdentifierScheme":"WEKO"}],"names":[{"name":"吉本, 一久"}]}]},"item_10_publisher_34":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"Kansai University"}]},"item_10_source_id_10":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12314657","subitem_source_identifier_type":"NCID"}]},"item_10_source_id_8":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"04532198","subitem_source_identifier_type":"ISSN"}]},"item_10_version_type_17":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Omura, Yasuhisa"}],"nameIdentifiers":[{"nameIdentifier":"28287","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"20298839","nameIdentifierScheme":"e-Rad","nameIdentifierURI":"https://nrid.nii.ac.jp/ja/nrid/1000020298839"}]},{"creatorNames":[{"creatorName":"Yoshimoto, Kazuhisa"}],"nameIdentifiers":[{"nameIdentifier":"28288","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2019-05-23"}],"displaytype":"detail","filename":"KU-1100-20080320-03.pdf","filesize":[{"value":"785.9 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"KU-1100-20080320-03.pdf","url":"https://kansai-u.repo.nii.ac.jp/record/11804/files/KU-1100-20080320-03.pdf"},"version_id":"e99e8efb-c9f0-4068-be61-d5764a5d6e7d"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"関西大学","subitem_subject_scheme":"Other"},{"subitem_subject":"Kansai University","subitem_subject_scheme":"Other"},{"subitem_subject":"SOI MOSFET","subitem_subject_scheme":"Other"},{"subitem_subject":"planar","subitem_subject_scheme":"Other"},{"subitem_subject":"single gate","subitem_subject_scheme":"Other"},{"subitem_subject":"minimum channel","subitem_subject_scheme":"Other"},{"subitem_subject":"ITRS road map","subitem_subject_scheme":"Other"},{"subitem_subject":"high speed","subitem_subject_scheme":"Other"},{"subitem_subject":"low standby power","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"departmental bulletin paper","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"Design Feasibility and Prospect of High-Performance Sub-50-nm-Channel Silicon-on-Insulator Single-Gate SOI MOSFET","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Design Feasibility and Prospect of High-Performance Sub-50-nm-Channel Silicon-on-Insulator Single-Gate SOI MOSFET"}]},"item_type_id":"10","owner":"1","path":["1629"],"pubdate":{"attribute_name":"公開日","attribute_value":"2018-02-20"},"publish_date":"2018-02-20","publish_status":"0","recid":"11804","relation_version_is_last":true,"title":["Design Feasibility and Prospect of High-Performance Sub-50-nm-Channel Silicon-on-Insulator Single-Gate SOI MOSFET"],"weko_creator_id":"1","weko_shared_id":1},"updated":"2023-05-15T14:52:29.063750+00:00"}