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アイテム
The Potential and the Drawbacks of Underlap Single-Gate Ultrathin SOI MOSFET
http://hdl.handle.net/10112/12437
http://hdl.handle.net/10112/12437fee661f0-ebff-47b5-a762-66db89f230f9
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
KU-1100-20080320-02.pdf (603.8 kB)
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| Item type | 紀要論文 / Departmental Bulletin Paper(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2018-02-20 | |||||
| タイトル | ||||||
| タイトル | The Potential and the Drawbacks of Underlap Single-Gate Ultrathin SOI MOSFET | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
| 資源タイプ | departmental bulletin paper | |||||
| 著者 |
Yoshioka, Yoshimasa
× Yoshioka, Yoshimasa× Hamada, Mitsuo× Omura, Yasuhisa |
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| 著者別名 | ||||||
| 識別子Scheme | WEKO | |||||
| 識別子 | 28285 | |||||
| 姓名 | 吉岡, 由雅 | |||||
| 著者別名 | ||||||
| 識別子Scheme | WEKO | |||||
| 識別子 | 28286 | |||||
| 姓名 | 大村, 泰久 | |||||
| 概要 | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | This paper describes the performance prospect of underlapped single-gate ultra-thin (USU) SOI MOSFET with a low-k or high-k gate dielectric from the viewpoint of both digital and analog applications. Increase in underlap length suppresses the threshold voltage variation as well as suppression of short-channel effects. In addition, the thickness of the SOI layer directly impacts the maximization of drive current (i. e., minimization of intrinsic delay time). Since the fringe capacitance is reduced in introduction of underlap region, effective gate capacitance is also reduced, while voltage gain of the device rises. Since apparent rise of cut-off frequency stems from the reduction of voltage gain, advancement of analog performance is inherentry limited. Use of a high-k gate dielectric basically reduces the gate-induced drain leakage (GIDL) current, while short-channel effects are degraded. In the case of very high dielectric constant, however, a very high electric-field region appearing far from the gate edge becomes a new source of high GIDL current. So, optimization of the dielectric constant of the gate insulator is required. | |||||
| 内容記述 | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | ELECTRICAL AND ELECTRONIC ENGINEERING, 50th anniversary edition | |||||
| 書誌情報 |
Science and technology reports of Kansai University = 関西大学理工学研究報告 巻 50, p. 17-27, 発行日 2008-03-20 |
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| ISSN | ||||||
| 収録物識別子タイプ | ISSN | |||||
| 収録物識別子 | 04532198 | |||||
| 書誌レコードID | ||||||
| 収録物識別子タイプ | NCID | |||||
| 収録物識別子 | AA12314657 | |||||
| 著者版フラグ | ||||||
| 出版タイプ | VoR | |||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
| 出版者 | ||||||
| 出版者 | Kansai University | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | 関西大学 | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Kansai University | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | MOSFET | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | silicon-on-insulator | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | underlap gate | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | GIDL | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | analog | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | high-k insulator | |||||
